As shown in FIG. 8, Patent Document 1 is an application which relates to a frequency bands analysis type subband echo canceller whose configuration includes a subband analysis process unit 11, an echo cancelling process unit 12 that performs a complex-valued process and a frequency bands synthesis process unit 13. In general, frequency bands analysis/synthesis is performed by a configuration of a combination of an analysis/synthesis filter using a low-pass filter referred to as a prototype filter on which an example of frequency response of a low-pass signal is shown in FIG. 9 and a DFT (Discrete Fourier Transform)/inverse DFT as shown in FIG. 10A and FIG. 10B, and by configuring a band-pass filter represented by exemplifying eight subbands Ba1 to Ba8 in FIG. 11. It should be noted that a broken line Sa is a curve representing frequency property of an input signal.
Further, explaining the above-mentioned signal processing device in FIG. 10A and FIG. 10B, it is configured such that a modulation side comprises an analysis filter process unit 21 including a circuit of signal division process series where number of subbands is K and decimation ratio is N and a DFT process unit 22 as shown in FIG. 10A, and demodulation side comprises an inverse DFT process unit 23 and an synthesis filter process unit 24 including a circuit of signal synthesis process series where number of subbands is K and decimation ratio is N as shown in FIG. 10B.
The subband echo canceller improves convergence of the echo canceller. Additionally, decimating of sampling in each band reduces the rate of the signal, thereby allowing the amount of arithmetic to be reduced. For instance, provided that the number of subbands is K and the decimation rate is N (sampling once from N times in each subband) as described above, N can theoretically be increased to K at the maximum. In this case, the signal rate in each subband becomes 1/K of the original signal rate.
A drawback of the method described in Patent Document 1 is that the subband signals become complex numbers as shown in FIG. 8 and an echo canceller compliant with complex numbers is required in the case of the subband echo canceller. In estimation of the amount of arithmetic, complex-valued arithmetic is for convenience' sake counted four times as many as real arithmetic. However, there is a possibility that a general-purpose processor not optimized for complex-valued arithmetic requires overhead processes such as data loading/storing, thereby greatly increasing the amount of processing.
Then, in Patent Document 2, as shown in FIG. 12, an SSB modulation process unit 31 performing a process referred to as SSB (Single Side Band) modulation, which is modulation suppressing a carrier wave and a single side band in amplitude modulation, is additionally provided, thereby making the subband signals real numbers. Subsequent to the SSB modulation process unit 31, an echo cancelling process unit 32 performing a real-valued process, and an SSB demodulation process unit 33 are provided, subsequent to which the above-mentioned subband synthesis process unit 13 is further provided.
In this configuration, the echo canceller can be what is compliant with real numbers. However, the theoretically maximum value of decimation ratio becomes K/2, thereby reducing an advantage of reduction in the amount of arithmetic due to reduction of signal speed in each subband. Provided that the number of subbands is K, WK is defined as a following equation (1), inputs are y(n) where n=0, . . . , K−1, and outputs are Yk where k=0, . . . , K−1, an equation of DFT is represented in a following equation (2). Provided that inputs are Yk where k=0, . . . , K−1 and outputs are y(n), n=0, . . . , K−1, an equation of the inverse DFT is represented in a following equation (3).
                    [                  Expression          ⁢                                          ⁢          1                ]                                                                      W          K                =                  ⅇ                      j            ⁡                          (                              2                ⁢                                  π                  /                  K                                            )                                                          (        1        )                                [                  Expression          ⁢                                          ⁢          2                ]                                                                                  Y            K                    =                                    ∑                              n                =                0                                            K                -                1                                      ⁢                                          y                ⁡                                  (                  n                  )                                            ⁢                              W                K                                  -                  kn                                                                    ⁢                                  ⁢                              k            =            0                    ,          1          ,          …          ⁢                                          ,                      K            -            1                                              (        2        )                                [                  Expression          ⁢                                          ⁢          3                ]                                                                                  y            ⁡                          (              n              )                                =                                    1              K                        ⁢                                          ∑                                  k                  =                  0                                                  K                  -                  1                                            ⁢                                                Y                  k                                ⁢                                  W                  K                  kn                                                                    ⁢                                  ⁢                              n            =            0                    ,          1          ,          …          ⁢                                          ,                      K            -            1                                              (        3        )            
When K is a power of two, FFT (Fast Fourier Transform) is applicable and the amount of arithmetic can be reduced.
Incidentally, the methods described in Patent Document 1 and Patent Document 2 are referred to as even types, and the center frequency ωk in each band is represented as a following equation (4) as shown in FIG. 11 that represents a case where the number of subbands is K=8.
                    [                  Expression          ⁢                                          ⁢          4                ]                                                                                  ω            k                    =                                    2              ⁢              π              ⁢                                                          ⁢              k                        K                          ⁢                                  ⁢                              k            =            0                    ,          1          ,          …          ⁢                                          ,                      K            -            1                                              (        4        )            
While in FIG. 11 the frequency properties are illustrated with the broken line where the sampling frequency is 2π and the input signal Sa is real numbers including frequency components 0 to π, with respect to them the even type cannot cover input signal components of 0 to π (a part of the broken line from 0 to π) properly by four subbands Ba1 to Ba4 up to K/2. In other words, five subbands including Ba5 are required.
On the other hand, according to the method referred to as an odd type, the centre frequency in each subband is represented in a following equation (5). A case where K=8 is shown in FIG. 13. In the figure, solid lines Bb1 to Bb8 are representing the frequency responses of eight subbands, and a broken line Sa is a curve representing the frequency property of an input signal.
                    [                  Expression          ⁢                                          ⁢          5                ]                                                                                  ω            k                    =                                                    2                ⁢                π                ⁢                                                                  ⁢                k                            K                        +                          π              K                                      ⁢                                  ⁢                              k            =            0                    ,          1          ,          …          ⁢                                          ,                      K            -            1                                              (        5        )            
The odd type can cover all of input signal components of 0 to π (a part of the broken line from 0 to π) by the four subbands Bb1 to Bb 4, and is more preferable in performance than the even type. As shown in FIG. 15A and FIG. 15B, the odd type is actualized by a GDFT process unit 51 that performs GDFT (Generalized DFT: Generalized Discrete Fourier Transformer) process on the basis of a following equation (6) including a frequency offset k0 and a time offset n0, and an inverse GDFT process unit 52 performing an inverse GDFT process on the basis of a following equation (7) where the frequency offset is set to k0=½. However, because use of this GDFT process increases the amount of arithmetic, a configuration including a DFT process and an inverse DFT process as shown in FIG. 14A and FIG. 14B that is described in Non-Patent Document 1 is typically used. More specifically, it is configured such that a modulation side includes the above-mentioned analysis filter process unit 21, a DFT preprocess unit 41, a DFT process unit 42 and a DFT postprocess unit 43 as shown in FIG. 14A, and a demodulation side includes an inverse DFT preprocess unit 44, an inverse DFT process unit 45, an inverse DFT postprocess unit 46, and the above-mentioned synthesis filter process unit 24 as shown in FIG. 14B.
In the configuration, the four process units, or the DFT preprocess unit 41 and the DFT postprocess unit 43 on the modulation side and the inverse DFT preprocess unit 44 and the inverse DFT postprocess unit 46 on the demodulation side, each includes complex-valued multiplication arithmetic on each subband. Furthermore, when the number of subbands K is a power of two, an FFT is applicable to the DFT process unit 42 and the inverse DFT process unit 45, thereby allowing the amount of arithmetic to be reduced.
                    [                  Expression          ⁢                                          ⁢          6                ]                                                                                  Y            K            GDFT                    =                                    ∑                              u                =                0                                            K                -                1                                      ⁢                                          y                ⁡                                  (                  n                  )                                            ⁢                              W                K                                                      -                                          (                                              k                        +                                                  k                          0                                                                    )                                                        ⁢                                      (                                          n                      +                                              n                        0                                                              )                                                                                      ⁢                                  ⁢                              k            =            0                    ,          1          ,          …          ⁢                                          ,                      K            -            1                                              (        6        )                                [                  Expression          ⁢                                          ⁢          7                ]                                                                                  y            ⁡                          (              n              )                                =                                    1              K                        ⁢                                          ∑                                  k                  =                  0                                                  K                  -                  1                                            ⁢                                                Y                  k                  GDFT                                ⁢                                  W                  K                                                            (                                              k                        +                                                  k                          0                                                                    )                                        ⁢                                          (                                              n                        +                                                  n                          0                                                                    )                                                                                                          ⁢                                  ⁢                              n            =            0                    ,          1          ,          …          ⁢                                          ,                      K            -            1                                              (        7        )            
Patent Document 1: JP 03-243020 A,
Patent Document 2: JP 3391144 B,
Non-Patent Document 1: S. Weiss. Analysis and Fast Implementation of Oversampled Modulated Filter Banks, Chapter 23 in John G McWhirter and Ian K. Proudler (eds.): Mathematics in Signal Processing V, IMA, Oxford University Press, pp. 263-274, March 2002.